In general, a data processing system includes a data processor functioning as a central processing unit (CPU) of the system, memory, and peripherals connected to the data processor. In many data processing systems, the data processor is a single-chip microcontroller which has on-chip memory and peripherals, but also is connected to external memory and external peripherals. The microcontroller executes various data processing instructions in software stored in internal and external memory. The peripherals perform various functions which may or must be implemented in external hardware circuitry, rather than by the microcontroller. For example, a phase locked loop (PLL) frequency synthesizer is a peripheral which includes circuitry able to function at radio frequency (RF). Processing of RF signals is beyond the capability of most microcontrollers, which are fabricated using complimentary metal-oxide-semiconductor (CMOS) technology. Therefore, a data processing system which processes RF signals requires an off-chip PLL frequency synthesizer peripheral.
Integrated circuit peripherals often include multiple on-chip registers, which must be initialized and periodically reprogrammed by the microcontroller. These peripherals also typically include a serial data port for receiving register data. The serial data port usually includes a clock pin, an enable pin, and a data pin, and data transfer usually conforms to a known serial protocol. In order to identify a selected one of the on-chip registers, conventional peripherals also require an address bit stream to be conducted on the data pin during the initialization or reprogramming. Address bit streams, however, add to the time required to update the peripheral's registers and increase software complexity.
One technique which eliminates the need for address bits in the serial bit stream was taught by David C. Babin in U.S. Pat. No. 5,146,577, entitled "Serial Data Circuit with Randomly-Accessed Registers of Different Bit Length," issued Sep. 8, 1992. Babin teaches a peripheral which selects an on-chip register by counting the number of data bits received during a data transfer, and transferring the data to a register which has a size corresponding to the number of data bits received.
However, an additional problem remains. In order to reduce data processor pin count in systems with multiple peripheral integrated circuits, peripherals are often cascadable. The data processor can use a single data pin to transmit data to any of a number of peripherals because each peripheral has a data output pin which connects to a data input pin of a subsequent peripheral. Writing to the registers based on the bit length can require very cumbersome software calculations because of bit alignment problems when the peripherals are cascaded.